- 8 Receive Channels
- 8 Transmit Channels
- FIFO Rx and Tx Buffers
- Time-Stamping of Receive Data
- Loop-back Support
- 256 ARINC word deep FIFO Buffer per Tx Channel
- Flexible Interrupts
- VMEbus D32 Interface
-Transmit Fault Insertion
-3.9 to 167KHz bit rate, software selectable
Occupying a single slot in a VME chassis, the Sy429VME-RT88 card offers an easy to
use, high performance, VME interface to 8Tx and 8Rx ARINC-429 channels with time-stamping
of receive data.
Each receive channel is individually software configured by writing data to a control
register. Data can be received with speeds between 3.9 and 500k bits/s. Received
data is time-stamped and stored in a FIFO buffer for easy access by the host processor.
Should an error occur during reception, the error is indicated by setting the parity
bit (bit 32) of the received data word. The cause of the error, whether due to parity,
bit count or word gap, can be identified from data logged in the Rx Error Status
Each transmit channel is individually software configured by writing data to a control
register. A choice of 125 separate data rates is available between 3.9 and 167 k
bits/s. The user has control over parity generation, inter-word gap and word length
(ie. Fault Insertion). Data for transmission is written to the appropriate Transmit
FIFO and, while there is data in the FIFO, transmission is automatic and continuous
with the pre-selected minimum gap between transmitted ARINC words. A separate FIFO,
with capacity for 256 ARINC-429 words, is provided for each transmit channel. A channel
enable/disable register is provided.
Each receiver is supported by a separate Time-Stamp FIFO. All received data is time-stamped
with a resolution selectable from 1µS to 255µS. The user can select between an internal
or external clock source. The timer can also be reset internally or externally and
read by the host processor.
The card provides for monitoring a wide range of system events. When a monitored
event occurs, a unique status word is generated and stored in a Status FIFO that
can be read by the host system. Interrupts can be generated whenever there is data
in the Event Status FIFO. The cause of the event is identified by reading the Event
The transmit channels can be internally looped back onto the receive channels for
test purposes. In this mode, the external outputs are disabled.
The card performs a 32-bit VME read/write cycle in less than 500nS.